The present invention relates to semiconductor integrated circuits and, more particularly, to arbitration circuits for arbitrating access to a shared resource, such as a memory.
Arbitration circuits are used in a variety of applications, such as in data communication circuits, for arbitrating access to memory. A typical data communication circuit has several data ports, and each port can have more than one channel such as a transmit channel and a receive channel. Each port or channel arbitrates for access to the memory through the arbitration circuit. A typical arbitration circuit has a central authority, which arbitrates between simultaneous requests for access based on some predetermined priority scheme, such as a round-robin, a first-come-first-serve or a forced-priority scheme.
While typical arbitration priority schemes are relatively straightforward to implement, it becomes difficult for the arbitration circuit to utilize the entire bandwidth of the memory as data transfer rates of communication channels continue to increase. For example, certain local area networks have data transfer rates exceeding one gigabit per second. With a large number of ports and each port having a relatively high data transfer rate, the timing requirements become very tight on the arbitration decision process. This also requires a very precise placement and route of the integrated circuits and circuit board on which the data communication circuit and memory are fabricated. In addition, the inefficiencies of the arbitration process may require the memory to be run at higher frequencies to support the required bandwidth. These design constraints often lead to higher fabrication costs and difficulties in achieving the desired bandwidths.
An improved arbitration circuit is desired, which can support higher bandwidths at normal operating frequencies.
One aspect of the present invention relates to an a method of arbitrating access to a memory, which has a plurality of banks. The method includes arbitrating with a plurality of processors. Each processor is associated with one of a plurality of data ports and has a plurality of arbitration cycles, including a current cycle and a most recent cycle preceding the current cycle. Each processor receives memory access requests from all of the data ports, wherein each memory access request is associated with one of the memory banks. Each processor selectively grants the data port associated with that processor access to the memory for the current cycle based on the banks associated with the memory access requests of each data port, the data port that was granted access to the memory during the preceding cycle, and the memory bank that was accessed during the preceding cycle.
Another aspect of the present invention relates to an arbitration circuit, which includes a shared resource, a plurality of data ports, data routing circuitry and a plurality of arbitration processors. Each data port has an access request output indicating whether the data port requests access to the shared resource. The data routing circuitry selectively couples the plurality of data ports to the shared resource based on the access request outputs. Each arbitration processor is associated with a respective one of the plurality of data ports and selectively forwards the access request output of that data port to the data routing circuit based on predetermined arbitration rules and a status of all of the access request outputs. Only one of the arbitration processors forwards the access request output of its associated data port to the data routing circuitry at one time.
Yet another aspect of the present invention relates to an arbitration circuit, which includes a memory and a plurality of data ports. The memory has a plurality of banks. Each data port has means for generating a memory access request, which is associated with one of the memory banks. The arbitration circuit rotates access to the memory from one of the data ports to the next in a circular sequence and modifies the sequence based on the banks associated with the memory access requests of each data port, the data port that was most recently granted access to the memory, and the bank that was most recently accessed.